Solar energy paper index
A Scalable All-to-All Reconfigurable Ising Solver Using Pulsed Time-Division Multiplexing
One-line summary
A solar energy research paper on A Scalable All-to-All Reconfigurable Ising Solver Using Pulsed Time-Division Multiplexing.
Engineering notes
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Chinese explanation / 中文解读
中文解读待补充：本站会优先为光伏效率、钙钛矿太阳能电池、储能技术、太阳能热利用、BIPV、并网技术等高价值论文补充中文说明。
Original abstract
Physics-based computing platforms, such as those based on the Ising model, are an important pillar of future hardware systems built for the artificial intelligence (AI) era. Such platforms show promise for solving nondeterministic polynomial (NP) time problems that are difficult for traditional processing units to solve efficiently as problem size grows. Here, we present a scalable optoelectronic Ising machine architecture, demonstrated with 64 all-to-all connected spins using pulsed time-division multiplexing. The 65 nm CMOS Ising chip integrates the coupling and nonlinear mechanisms in an active area of 3.1 mm2, eliminating the need for benchtop equipment within the loop. The feedback loop of the Ising machine is closed using a compact high-bandwidth, low-loss optical fiber, seamlessly combining optical scalability with the ultradense reconfigurability of integrated electronics. The chip operates at 1 GHz with 4-bit coupling weights and is benchmarked with NP-complete Boolean satisfiability problems consisting of three literals (3-SAT) and clause-to-variable ratios of 32/32, 40/24, and 48/16. Nanosecond annealing times represent at least a three order-of-magnitude improvement over previously reported all-to-all connected works. Time and energy to solutions for 100% 3-SAT clause accuracy are as low as 7.4 us and 2.9 uJ, respectively, achieving more than an order-of-magnitude decrease in time and energy to solution compared to the state of the art. All-to-all connection is demonstrated using MaxCut problems with 100% graph densities. The chip's ability to effectively solve 2-, 3-SAT, and MaxCut problems highlights its reconfigurability and versatility. Furthermore, combining mature CMOS integration with scalable photonic links allows for significant reduction in computation time and energy, addressing the pressing requirements of AI and future hyperscale datacenters.
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